1. Field of the Invention
The present invention relates to a booster circuit, and more particularly to a booster circuit included in a semiconductor integrated circuit and operating based on a multiphase clock.
2. Description of the Background Art
A nonvolatile memory, such as a flash EEPROM, or a microcomputer including such a memory requires a voltage higher than an externally-supplied power supply voltage in order to perform erase/program operations (hereinafter, collectively referred to as a “rewrite operation”) or a read operation on the nonvolatile memory. The voltage required for such operations is supplied from a booster circuit included in the nonvolatile memory or the like and generating a plurality of boosted voltages. As the booster circuit, a four-phase clock driven threshold balancing-type booster circuit, which is operable at a low voltage level to effectively boost the voltage level, is widely used.
FIG. 16 is a diagram illustrating the configuration of a conventional four-phase clock driven booster circuit. The booster circuit shown in FIG. 16 includes a first booster block 48 for generating a voltage Pout1 higher than a power supply voltage, and a second booster block 49 for generating a voltage Pout2 higher than the voltage Pout1. The first booster block 48 includes an oscillation circuit 10, a plurality of four-phase clock generation circuits 29, pump circuits 69, the number of which is equal to the number of four-phase clock generation circuits 29, and a detection circuit 70. The second booster block 49 is configured in a manner similar to the first booster block 48.
Each circuit included in the first booster block 48 operates as described below. The oscillation circuit 10 outputs a plurality of oscillation clocks 100 different in phase from each other. The four-phase clock generation circuits 29 each generate a four-phase clock 209, which is composed of four clocks different in phase from each other, based on one of the oscillation clocks 100 (e.g., OSC1). The pump circuits 69 each generate a voltage Pout1, which is higher than a power supply voltage, based on the four-phase clock 209 generated by one of the four-phase clock generation circuits 29. In order to control the voltage Pout1 outputted from the pump circuits 69 so as to become predetermined voltage (hereinafter, referred to as “target voltage”), the detection circuit 70 controls on/off operations of the oscillation circuit 10 based on the level of the voltage Pout1. In the detection circuit 70, the target voltage is switched between, for example, high and low levels in accordance with a voltage setting signal ACTH.
The oscillation circuit 10 includes, for example, a ring oscillator in which one NAND gate and an even number of inverters are connected to form a ring (see FIG. 2 which will be described later). The four-phase clock generation circuits 29 are each, for example, a circuit in which inverters and selection circuits 22 are connected together as shown in FIG. 17. The selection circuits 22 each output input A when input S is at a low (L) level, and input B when the input S is at a high (H) level (see FIG. 4 which will be described later). The four-phase clock generation circuits 29 each include delay circuits 28, each being composed of a plurality of inverters connected in series with each other. A time period of delay caused in each of the delay circuits 28 is assumed to be Tcs.
The pump circuits 69 are each, for example, a circuit in which four booster cells 68 and 62-64 are connected in series with each other as shown in FIG. 18A. The booster cell 64 in the last stage has an output terminal connected to a rectifier transistor 65. As shown in FIG. 18A, each of the booster cells 68 and 62-64 is coupled to and driven by two clocks in the four-phase clock 209 generated by one of the four-phase clock generation circuits 29.
The booster cells 68 and 62-64 are booster cells of a type as shown in FIG. 18B, for example. The booster cells 68 and 62-64 each include an N-channel charge transfer transistor M1, an N-channel switch transistor M2, booster capacitors C1 and C2, and a voltage reset circuit 67. The voltage reset circuit 67 cause a gate terminal of the charge transfer transistor M1 and a ground terminal to become nonconductive when a voltage resetting signal ACTR inputted from an R terminal is inactive, and causes both of the terminals to become conductive when the signal is active. Thus, when the voltage resetting signal ACTR becomes active, a gate voltage Vg applied across the charge transfer transistor M1 is reset to a ground voltage VSS. Such a voltage reset circuit 67 is realized by an NMOS transistor M3 in which a source terminal is grounded, a drain terminal is connected to the gate terminal of the charge transfer transistor M1, and the voltage resetting signal ACTR is applied to a gate terminal.
Referring to FIG. 19, a four-phase clock generation method for use in the conventional booster circuit as configured in the above-described manner is described. The oscillation circuit 10 starts operating when the level of a clock enable signal CP_EN inputted from an EN terminal becomes “H”, and sequentially outputs, as oscillation clocks 100, n signals OSC1 to OSCn so as to be delayed in increments of a predetermined period of time (a time period of delay Tos shown in FIG. 19).
In an i'th four-phase clock generation circuit 29 as shown in FIG. 17 (where i is an integer in the range of 1 to n), when a signal OSCi outputted from the oscillation circuit 10 falls, a clock CLKG1iS falls. Upon the fall of the clock CLKG1iS, a clock CLKT1iS rises. After a time period of delay Tcs since the rise of the clock CLKT1iS, which is caused by the delay circuit 28, a clock CLKT2iS falls. Upon the fall of the clock CLKT2iS, a clock CLKG2iS rises. After a lapse of a time period of charge transfer Ttr, the clock OSCi rises, and the clock CLKG2iS falls. Upon the fall of the clock CLKG2iS, the clock CLKT2iS rises. After a time period of delay Tcs from the rise of the clock CLKT2iS, which is caused by the delay circuit 28, the clock CLKT1iS falls. Upon the fall of the clock CLKT1iS, the clock CLKG1iS rises. In this manner, in the i'th four-phase clock generation circuit 29, the four clocks CLKG1iS, CLKT1iS, CLKT2iS, and CLKG2iS, which are different in phase from each other, are generated based on the signal OSCi outputted from the oscillation circuit 10. Note that FIG. 19 shows, by way of example, how an n'th four-phase clock generation circuit 29 generates the four clocks CLKG1nS, CLKT1nS, CLKT2nS, and CLKG2nS based on a signal OSCn outputted from the oscillation circuit 10.
An i'th pump circuit 69 performs voltage boosting based on the four clocks CLKG1iS, CLKT1iS, CLKT2iS, and CLKG2iS outputted from the i'th four-phase clock generation circuit 29, and outputs a voltage Pout1 higher than a power supply voltage. The pump circuit 69 transfers electric charge for performing the voltage boosting during a period in which the level of the clock CLKG1iS or CLKG2iS is “H”. Accordingly, the efficiency of the voltage boosting increases as the period becomes longer (i.e., as the time period of charge transfer Ttr becomes longer).
The detection circuit 70 has a target voltage higher than a power supply voltage. The detection circuit 70 sets a clock enable signal CP_EN to “H” level when the voltage Pout1 outputted from the pump circuits 69 is lower than the target voltage, and sets the signal CP_EN to “L” level when the voltage Pout1 is higher than the target voltage. While the signal CP_EN is at “H” level, the oscillation circuit 10 is active, and accordingly the pump circuits 69 perform voltage boosting, so that the voltage Pout1 rises. On the other hand, while the signal CP_EN is at “L” level, the oscillation circuit 10 is inactive, and accordingly the pump circuits 69 cease the voltage boosting, so that the voltage Pout1 does not rise. Thus, the voltage Pout1 outputted from the pump circuits 69 are controlled so as to coincide with the target voltage.
As described above, in a conventional booster circuit, each pump circuit 69 operates based on one oscillation clock 100 outputted from the oscillation circuit 10 (see, for example, Japanese Laid-Open Patent Publication No. 2000-331489).
Next, the pump circuits 69 included in a conventional booster circuit (FIGS. 18A and 18B) are described in detail. When the booster circuit is activated, the voltage resetting signal ACTR is held at “L” level, so that the NMOS transistor M3 included in the voltage reset circuit 67 becomes nonconductive. The pump circuit 69 outputs four clocks CLKG1iS, CLKT1iS, CLKT2iS, and CLKG2iS, each being a square wave which periodically alternates between “H” and “L” levels (see FIG. 19). Note that periods for “H” and “L” levels each have a predetermined length. As shown in FIG. 18A, the four clocks are inputted to the booster cells 68 and 62-64.
When the four-phase clock is supplied, the pump circuit 69 transfers electric charge accumulated in a booster capacitor C1 included in the booster cell 68 in the first stage to a booster capacitor C1 included in the booster cell 62 in the second stage. Then, the electric charge is transferred to a booster capacitor C1 included in the booster cell 63 in the third stage, and further to a booster capacitor C1 included in the booster cell 64 in the fourth stage. When the electric charge is sequentially transferred from one booster capacitor C1 to another, the clocks CLKT1iS and CLKT2iS are changed from a ground voltage level to a power supply voltage level at a predetermined time, whereby it is possible to suppress a drop of the boosted voltage transferred from a circuit in a preceding stage. Thereafter, the boosted voltage is transferred to a booster capacitor C1 in a next stage, where the clocks CLKG1iS and CLKG2iS are changed from a ground voltage level to a power supply voltage level at a predetermined time, so that the boosted voltage is further boosted. Thus, it is possible to obtain a voltage higher than the voltage outputted from the circuit in the preceding stage. By repeating this series of operations, it is possible to obtain a desired voltage higher than a power supply voltage VCC.
The voltage Pout1 to be outputted from the first booster block 48 is controlled by the detection circuit 70 so as to be kept at the target voltage level. As shown in FIG. 16, the detection circuit 70 receives a voltage setting signal ACTH for changing the level of the target voltage. When a relatively high voltage (e.g., 10V) is required, such as when a rewrite operation is performed on a flash EEPROM, the voltage setting signal ACTH is set at “H” level, for example. In such a case, the target voltage of the detection circuit 70 is 10V, and the voltage Pout1 to be outputted from the first booster block 48 is controlled so as to be 10V. On the other hand, when a relatively low voltage (e.g., 5V) is required, such as when a read operation is performed on a flash EEPROM, the voltage setting signal ACTH is set at “L” level, for example. In such a case, the target voltage of the detection circuit 70 is 5V, and the voltage Pout1 to be outputted from the first booster block 48 is controlled so as to be 5V. In this manner, by changing the level of the voltage setting signal ACTH, it is possible to switch the voltage Pout1 to be outputted from the booster circuit between a plurality of levels depending on modes of operation.
However, in the case where the mode suddenly transits from rewrite to read, for example, the pump circuit 69 might encounter a problem as described below when the level of the target voltage is changed. If the target voltage is changed from high level to low level, a source voltage Vs and a drain voltage Vd are suddenly decreased in a charge transfer transistor M1 included in the fourth-stage booster cell 64, so that the voltages become substantially equal to each other. Accordingly, regardless of the states of the clocks CLKG1iS and CLKT1iS, the switch transistor M2 is brought into a constant cut-off state, so that a gate voltage Vg is kept high level in the charge transfer transistor M1. As a result, regardless of the states of the clocks CLKG1iS and CLKT1iS, agate-source voltage Vgs in the charge transfer transistor M1 becomes higher than a threshold voltage Vt (e.g., about 0.5V) of the charge transfer transistor M1, so that the charge transfer transistor M1 is brought into a constant conductive state. Accordingly, as in the fourth-stage booster cell 64, a source voltage Vs and a drain voltage Vd are suddenly decreased in a charge transfer transistor M1 included in the third-stage booster cell 63, so as that each node included in the third-stage booster cell 63 is brought into the same state as each node included in the booster cell 64. As a result, the charge transfer transistor M included in the third-stage booster cell 63 is also brought into a constant conductive state. The same occurs to the second-stage booster cell 62 and the first-stage booster cell 68, so that each node included in the second-stage booster cell 62 and each node included in the first-stage booster cell 68 are brought into a state as described above. The above problem is also encountered when the power supply voltage is changed to low level simultaneously as changing the target voltage from high level to low level. In this case, indeed, the above problem might be readily encountered. If the above problem is encountered, a desired voltage level cannot be obtained after the level of the target voltage is changed, so that the current supply capability of the booster circuit is deteriorated. The above-described problem is further readily encountered if the operation voltage of the booster circuit is increasingly reduced.
Therefore, in order to prevent the above problem, each of the booster cells 68 and 62-64 include the voltage reset circuit 67. The voltage reset circuit 67 is supplied with a voltage resetting signal ACTR inputted from an R terminal of a corresponding one of the booster cells. The voltage resetting signal ACTR is placed in an active state (“H”) only for a predetermined period of time (e.g., about 10 nanoseconds (ns)) when the voltage setting signal ACTH varies. Consequently, only for a period in which the voltage resetting signal ACTR is placed in an active state, a gate-source voltage (the level of which is equal to the level of the power supply voltage VCC, e.g., 2.5V) in an NMOS transistor M3 included in the voltage reset circuit 67 exceeds a threshold voltage (e.g., 0.5V) of the NMOS transistor M3, so that the NMOS transistor M3 becomes conductive. Thus, the level of a gate voltage Vg in the charge transfer transistor M1 included in each of the booster cells 68 and 62-64 is reset to the level of the ground voltage VSS. Thereafter, by changing the voltage resetting signal ACTR so as to be in an inactive state (“L”), the NMOS transistor M3 is caused to become nonconductive. Accordingly, even if the gate voltage is gradually boosted in the charge transfer transistor M1, boost charge is not lost, and therefore the pump circuit 69 is able to normally perform voltage boosting. In this manner, by providing the voltage reset circuit 67, it becomes possible to prevent the problem where the charge transfer transistor M1 is brought into a constant conductive state.
The above-described conventional booster circuit has problems as described below. In the conventional booster circuit, four-phase clocks 209 to be supplied to pump circuits 69 are separately generated by their corresponding four-phase clock generation circuits 29 based on one oscillation clock 100 outputted from the oscillation circuit 10. Also, the cycle Tosc of the oscillation clock 100 is determined by the configuration of the oscillation circuit 10 (specifically, a time period of delay caused by inverters and capacitors which are included in a ring oscillator), whereas a time period of delay Tcs between the clocks CLKT1iS and CLKT2iS is determined by the configuration of a corresponding one of the four-phase clock generation circuits 29 (specifically, a time period of delay caused by the delay circuit 28). There are two reasons that the cycle Tosc and the time period of delay Tcs are determined by different circuits. First, it is necessary to separately cancel power supply voltage characteristics, etc., of the cycle Tosc of the oscillation clock 100. Second, a time period of delay caused by each of the four-phase clock generation circuit 29 is several nanoseconds, and the number of required four-phase clock generation circuits 29 is the same as the number of pump circuits 69, so that the four-phase clock generation circuits 29 are each required to be small in size. However, in the booster circuit where the cycle Tosc and the time period of delay Tcs are separately determined by different circuits, the cycle Tosc and the time period of delay Tcs may or may not become proportional to each other depending on operating conditions, such as the power supply voltage, variations in process, temperature fluctuations, etc. Accordingly, under given operating conditions, the time period of charge transfer Ttr becomes shorter, resulting in a reduction of voltage boost efficiency. For the above reasons, it is also difficult to increase the frequency of the oscillation clock 100.
Also, in the conventional booster circuit, both the first booster block 48 and the second booster block 49 include the oscillation circuit 10 and the four-phase clock generation circuits 29, and therefore the circuit size is large. Also, if the first booster block 48 and the second booster block 49 are operated with the same four-phase clock 209, current flows to the booster blocks at the same time, resulting in an increase of peak current.
Also, in the conventional booster circuit, when the level of the clock enable signal CP_EN is changed to “L”, four-phase clocks 209 to be supplied to all pump circuits 69 are simultaneously held at the same level. In such a case, regardless of the states of the pump circuits 69, all the four-phase clocks 209 are held at the same level, so that the peak current is increased compared to the normal state. Moreover, if the voltage Pout2 is higher than the voltage Pout1, the rise time of the voltage Pout2 becomes longer because the current supply capability of the second booster block 49 is lower than that of the first booster block 48.
Also, as described above, the booster cells 68 and 62-64 each include the voltage reset circuit 67 in order to prevent the problem where the charge transfer transistor M1 is brought into a constant conductive state. However, in the first-stage booster cell 68, the drain terminal and substrate node of the switch transistor M2 are held at the power supply voltage VCC, and therefore, while the voltage resetting signal ACTR is in an active state, if the level of the gate voltage in the charge transfer transistor M1 is controlled so as to become close to the level of the ground voltage, current flows from the power supply VCC to the gate terminal of the charge transfer transistor M1 via a forward-biased PN junction between the substrate and a source node in the switch transistor M2. Accordingly, in addition to the voltage reset circuit 67, the conventional booster circuit requires a time control circuit for controlling a period of time for which the voltage resetting signal ACTR is activated. As a result, the circuit size of the booster circuit is increased by the size of the time control circuit.